This document will describe the work done under the PRACE-4IP extension. This task is dedicated to provide useful information on application *performance and energy usage* on next generation systems on the path towards exacsale. It will be caried out running the accelerated UEABS on PCP systems to obtain energy metrics on *OpenPower+GPU, Xeon Phi and FPGA*.
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* a mailing list: prace-4ip-wp7.extension@fz-juelich.de, subscribe here: `mailing list registration page`_.
* this documentation.
The following methodology will be followed to lead this task:
The following timeline will be followed to lead this task:
#. white paper indicating what applications will be run on which prototypes (meeting the PRACE milestone **MS33 due by August 2017/M4**)
#. grant access to machines (cut off September 2017 )
#. run benchmarks (cut off October/November)
#. run codes (cut off October/November)
#. gather results and report *Applications Performance and Energy Usage* (this adresses the PRACE deliverable **D7.7 due by December 2017/M8**)
PCP systems availables
----------------------
This section describes the systems where codes owners have been granted access.
The table :ref:`table-pcp-systems` sums up systems and availability:
.. note:: More detailed information can be found for :ref:`e4_gpu`, :ref:`atos_knl` and :ref:`maxeler_fpga` systems. It includes, hardware description, registration procedures, and energy hardware and tool information.
Code definition
---------------
Two sets of codes will be run. One will focus on giving metrics on multiple machines for UEABS codes while the other will focus on porting specific kernels to the KNL machine sampling energy impact on modification.
UEABS
^^^^^
The table :ref:`table-code-definition` shows all codes available with UEABS (regular and accelerated). It states for each codes, tageted architechures and BCOs. Note that due to tight deadlines, efforts to port codes to new architechures will have to be minimal.
.. _table-code-definition:
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| Code name +--------------+----------+------+ 4IP-extension BCO +
.. note:: The registration process included whithin is aimed at BCOs only.
Power8 + GPU
^^^^^^^^^^^^
This machine has been designed by `E4 computer engineering`_ and is hosted at CINECA_ in Bologna, Italy.
.. note:: In order to access the machine BCO should register on the `CINECA user datatabase`_ and ask `Victor Cameo Ponz`_ to be added to the 4IP-extension project.
Compute technology
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Hardware features fat-nodes with the following design:
* 45 nodes with x2 IBM POWER8 processors and x4 NVIDIA P100 GPU
* intranode comunications integrated using NVLink
* extranode comunications integrated using Infiniband ERD interconnect
* CPU and GPU liquid cooling based on CoolIT_ solution
Energy sampling technology
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FPGA
^^^^
This machine has been designed by MAXELER_ and is hosted at JSC_ in Julich, Germany.
Compute technology
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This small pilot system features:
- 4 MPC-H servers including 2x MAX5 DFE and 2x Intel Xeon processors
