NEX dedicated pages for each machine

doc/sphinx/atos_knl.rst

+.. _atos_knl:
+
 Xeon Phi
 ^^^^^^^^
 
@@ -5,7 +7,7 @@ This machine has been designed by `Atos/Bull`_ and is hosted at CINES_ in Montpe
 
 .. note::
 
-    In order to access the machine BCO should fill the CINES login opening form: `odt <cines-login-form-odt_>`_ or `rtf <cines-login-form-rtf_>`_.
+    In order to access the machine BCOs should fill the CINES login opening form: `odt <cines-login-form-odt_>`_ or `rtf <cines-login-form-rtf_>`_.
     Use the following information to fill project related fields:
 
      - project outside DARI
@@ -26,3 +28,9 @@ Hardware features the following nodes:
 Energy sampling technology
 """"""""""""""""""""""""""
 
+
+.. _cines-login-form-odt: https://www.cines.fr/wp-content/uploads/2014/01/opening_renewal_login_2017.odt
+.. _cines-login-form-rtf: https://www.cines.fr/wp-content/uploads/2014/01/opening_renewal_login_2017.rtf
+.. _Atos/Bull: https://bull.com/
+.. _CINES: https://www.cines.fr/
+.. _Victor Cameo Ponz: cameo+4ip-extension@cines.fr

doc/sphinx/e4_gpu.rst

+.. _e4_gpu:
+
+Power8 + GPU
+^^^^^^^^^^^^
+
+This machine has been designed by `E4 computer engineering`_ and is hosted at CINECA_ in Bologna, Italy.
+
+.. note:: In order to access the machine BCO should register on the `CINECA user datatabase`_ and ask `Victor Cameo Ponz`_ to be added to the 4IP-extension project.
+
+Compute technology
+""""""""""""""""""
+
+Hardware features fat-nodes with the following design:
+ * 45 nodes with x2 IBM POWER8 processors and x4 NVIDIA P100 GPU
+ * intranode comunications integrated using NVLink
+ * extranode comunications integrated using Infiniband ERD interconnect
+ * CPU and GPU liquid cooling based on CoolIT_ solution
+
+Energy sampling technology
+""""""""""""""""""""""""""
+
+.. _E4 computer engineering: https://www.e4company.com
+.. _CINECA: http://hpc.cineca.it/
+.. _CINECA user datatabase: https://userdb.hpc.cineca.it/
+.. _CoolIT: https://www.coolitsystems.com/
+.. _Victor Cameo Ponz: cameo+4ip-extension@cines.fr
+

doc/sphinx/maxeler_fpga.rst

+.. _maxeler_fpga:
+
+
+FPGA
+^^^^
+
+This machine has been designed by MAXELER_ and is hosted at JSC_ in Julich, Germany.
+
+Compute technology
+""""""""""""""""""
+
+This small pilot system features:
+ - 4 MPC-H servers including 2x MAX5 DFE and 2x Intel Xeon processors
+
+Energy sampling technology
+""""""""""""""""""""""""""
+
+
+.. _MAXELER: http://maxeler.com/
+.. _JSC: http://www.fz-juelich.de/ias/jsc/EN/Home/home_node.html